基于解串器和1gbps电路的325gbps cdr的sopc的构建和方法-英文翻译.rar

Abstract
The SoPC (System on a Programmable Chip) aspects of the Stratix GX™ FPGA with 3.125Gbps SERDES are described. The FPGA was fabricated on a 0.13um, 9-layer
metal process. The 16 high-speed serial transceiver channels with Clock Data Recovery (CDR) provides 622-megabits per second (Mbps) to 3.125-Gbps full-duplex transceiver operation per channel. Another challenge described, is the implementation of 39 source-synchronous channels at 100Mbps to 1Gbps, utilizing Dynamic Phase Alignment (DPA). The implementation and integration of the FPGA logic array (with its own Hard IP) with the CDR and DPA channels involved grappling with SoC design
issues and methodologies.

摘要
带有3.125Gbps 解串器的Stratix GX™ FPGA 的Sopc(可编程芯片)方面进行了描述。
FPGA是虚构的9层0.13um金属的过程。16个带时钟数据恢复(CDR)的高速串行收发渠道提供622M每秒(Mbps)到每通道3.125-Gbps的全双工收发器操作。另一个难题是对39个从100Mbps到1Gbps的同步源通道利用动态相位定位（DPA）的描述,FPGA逻辑阵列(有自己的固定IP)与CDR和DPA通道涉及克服SoC的设计问题和方法的实施和整合。